1. Field of the Invention
The present invention relates to a MOS-technology power device chip and package assembly.
2. Discussion off the Related Art
Conventional MOS-technology power device chips (e.g. power MOSFETs) include a semiconductor layer in which several millions of elementary vertical MOSFET units are integrated; an insulated gate layer having a mesh structure is superimposed over the semiconductor layer to form a common gate electrode for all the elementary MOSFET units, and is connected to a metal pad. The insulated gate layer is covered by an insulating material layer in which contact windows to underlying source regions of all the elementary MOSFET units are opened. The chip surface is almost completely covered by a metal layer which, through the windows in the insulating material layer, contacts the source regions of all the elementary MOSFET units, thus forming a source electrode of the power MOSFET; the bottom surface of the chip is also covered by a metal layer forming a drain electrode of the power MOSFET. After the device chip has been inserted in the desired package, the gate metal pad, the source metal layer and the drain metal layer are bonded to respective wires which are in turn connected to external pins of the package, for Electrical and mechanical connection to traces on a Printed Circuit Board (PCB).
The package must be a power package, and must exhibit high power capability and high power density. The package pins, expecially those forming the external source and drain terminals of the power MOSFET, conduct very high currents.
An important aspect to be considered when choosing a power package is represented by the parasitic electrical components introduced by the package. In fact, the parasitic resistance of the bonding wires and of the package pins causes an increase in the ourput resistance of the power device, which in turn causes an increase in power dissipation, while the parasitic inductance of the bonding wires and of the package pins is responsible for inductive switching problems.
A possible solution calls for bonding to the source metal layer of the device chip more than one wire in this way, due to the parallel connection of the parasitic. resistance and inductance are reduced. The problem is that this solution is not reliable, because there is no way during device testing to ascertain how many wires arc effectively in contact with the source electrode on the chip:
It is also known that even in the power device field there is a trend toward Surface Mount Technology (SMT) packages, since they allow an increase in productivity. They also reduce the PCB area, and they allow production of PCBs with components mounted on both sides. For example, an SMT multipin power package, known under the commercial name "Power SO-10TM", has recently been developed for Power Integrated. Circuits (PICs), which have multiple outputs.
In view of the state ortho art described, it is an object of the present invention to provide a MOS-technology power device chip and package assembly overcoming at least the abovementioned drawbacks.